Using The Tx Phase-Alignment Circuit To Bypass The Buffer - Xilinx Virtex-6 FPGA User Manual
Gtx transceivers
Hide thumbs
Also See for Virtex-6 FPGA:
- Manual (381 pages) ,
- User manual (148 pages) ,
- Getting started manual (77 pages)
Table of Contents
Advertisement
Chapter 3: Transmitter
Table 3-19: TX Buffer Bypass Attributes (Cont'd)
Attribute
TX_XCLK_SEL
TXOUTCLK_CTRL
Using the TX Phase-Alignment Circuit to Bypass the Buffer
To use the TX phase-alignment circuit, follow these steps:
1.
2.
3.
4.
5.
6.
Table 3-20: Number of Required TXUSRCLK2 Clock Cycles for Driving
TXPMASETPHASE High
The phase-alignment procedure must be redone if any of the following conditions occur:
www.BDTIC.com/XILINX
158
Type
String
Selects the clock used to drive the clock domain in the PCS following
the TX buffer. When using the TX buffer, this attribute is set to TXOUT.
The attribute must be set as follows:
TXOUT: Use when TX_BUFFER_USE = TRUE
TXUSR: Use when TX_BUFFER_USE = FALSE
String
This attribute is the multiplexer select signal from the TX Fabric Clock
Output Control block (see
TXOUTCLKPCS (DRP value 000)
TXOUTCLKPMA_DIV1 (DRP value 001)
TXOUTCLKPMA_DIV2 (DRP value 010)
TXPLLREFCLK_DIV1 (DRP value 011)
TXPLLREFCLK_DIV2 (DRP value 100)
OFF_LOW (DRP value 101)
OFF_HIGH (DRP value 110)
Set the following attributes with their values as follows:
a.
Set TXOUTCLK_CTRL to use either TXPLLREFCLK_DIV2 or
TXPLLREFCLK_DIV1
b. Set TX_XCLK_SEL to TXUSR
c.
Set TX_BUFFER_USE to FALSE
d. Set TX_PMADATA_OPT to 1'b1
After power-on, make sure TXPMASETPHASE and TXENPMAPHASEALIGN are
driven Low.
Apply GTXTXRESET and wait for TXRESETDONE to go High.
Drive TXENPMAPHASEALIGN High.
Keep TXENPMAPHASEALIGN High unless the phase-alignment procedure must be
repeated. Driving TXENPMAPHASEALIGN Low causes phase alignment to be lost.
Wait 32 TXUSRCLK2 clock cycles and then drive TXPMASETPHASE High.
Wait the number of required TXUSRCLK2 clock cycles as specified in
then drive TXPMASETPHASE Low. The phase of the PMACLK is now aligned with
TXUSRCLK.
TXPLL_DIVSEL_OUT
1
2
4
www.xilinx.com
Description
Figure
3-28).
TXUSRCLK2 Wait Cycles
8,192
16,384
32,767
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Table
3-20, and
Advertisement
Table of Contents
