Rx Analog Front End; Functional Description - Xilinx Virtex-6 FPGA User Manual

Chapter 4: Receiver
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RX Analog Front End

Functional Description

The RX analog front end (AFE) is a high-speed current-mode input differential buffer. It
has the following features
•
•
•
X-Ref Target - Figure 4-2
Board
~100 nF
MGTAVTT_*
~100 nF
www.BDTIC.com/XILINX
184
RX Margin Analysis, page 210
RX Polarity Control, page 213
RX Oversampling, page 214
RX Pattern Checker, page 215
RX Byte and Word Alignment, page 217
RX Loss-of-Sync State Machine, page 226
RX 8B/10B Decoder, page 228
RX Buffer Bypass, page 231
RX Elastic Buffer, page 238
RX Clock Correction, page 240
RX Channel Bonding, page 247
RX Gearbox, page 256
RX Initialization, page 261
FPGA RX Interface, page 269
Configurable RX termination voltage
Bypassable on-chip coupling capacitors
Calibrated termination resistors
FPGA
MGTAVTT_*
ESD Diodes
nominal
50Ω
nominal
MGTAVTT_*
50Ω
ESD Diodes
Figure 4-2: RX AFE Block Diagram
www.xilinx.com
nominal 7 pF
RCV_TERM_VTTRX
RCV_TERM_GND
AC_CAP_DIS
GND
FLOAT
nominal 7 pF
Virtex-6 FPGA GTX Transceivers User Guide
V CM
nominal
2/3 MGTAVTT_*
50 KΩ
nominal
50 KΩ
UG366_c4_02_081109
UG366 (v2.5) January 17, 2011