Enabling And Disabling 8B/10B Encoding; Tx Gearbox; Functional Description; Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

Chapter 3: Transmitter
Table 3-12: TX Encoder Ports (Cont'd)
Port
TXKERR[3:0]
TXRUNDISP[3:0]
There are no TX encoder attributes.

Enabling and Disabling 8B/10B Encoding

To enable the 8B/10B encoder, TXENC8B10BUSE must be driven High. To disable the
8B/10B encoder on a given GTX transceiver, TXENC8B10BUSE must be driven Low. When
the encoder is turned off, the operation of the TXDATA port is as described in
Interface, page

TX Gearbox

Functional Description

Some high-speed data rate protocols use 64B/66B encoding to reduce the overhead of
8B/10B encoding while retaining the benefits of an encoding scheme. The TX gearbox
provides support for 64B/66B and 64B/67B header and payload combining. The
Interlaken interface protocol specification uses the 64B/67B encoding scheme. Refer to the
Interlaken specification for further information. The Interlaken specification can be
downloaded from: http://www.cortina-systems.com/news/interlaken. The TX gearbox
only supports 2-byte and 4-byte interfaces. A 1-byte interface is not supported.
Scrambling of the data is done in the FPGA logic. The Virtex-6 FPGA GTX Transceiver
Wizard has example code for the scrambler.

Ports and Attributes

Table 3-13
www.BDTIC.com/XILINX
146
Dir Clock Domain
Out TXUSRCLK2 TXKERR indicates if an invalid code for a K character was
specified.
Out TXUSRCLK2 TXRUNDISP indicates the current running disparity of the
8B/10B encoder. This disparity corresponds to TXDATA clocked
in several cycles earlier.
128.
defines the TX gearbox ports.
www.xilinx.com
Description
TXKERR[3] corresponds to TXDATA[31:24]
TXKERR[2] corresponds to TXDATA[23:16]
TXKERR[1] corresponds to TXDATA[15:8]
TXKERR[0] corresponds to TXDATA[7:0]
TXRUNDISP[3] corresponds to previous TXDATA[31:24] data
TXRUNDISP[2] corresponds to previous TXDATA[23:16] data
TXRUNDISP[1] corresponds to previous TXDATA[15:8] data
TXRUNDISP[0] corresponds to previous TXDATA[7:0] data
Virtex-6 FPGA GTX Transceivers User Guide
FPGA TX
UG366 (v2.5) January 17, 2011