Ports And Attributes; Rx Pattern Checker; Functional Description - Xilinx Virtex-6 FPGA User Manual

Ports and Attributes

Table 4-29
Table 4-29: RX Oversampling Ports
Port
RXENSAMPLEALIGN
RXOVERSAMPLEERR
Table 4-30
Table 4-30: RX Oversampling Attributes
Attribute
PMA_RX_CFG
RX_OVERSAMPLE_MODE
RXPLL_DIVSEL_OUT

RX Pattern Checker

Functional Description

The GTX receiver includes a built-in PRBS checker. This checker can be set to check for one
of four industry-standard PRBS patterns. The checker is self-synchronizing and works on
the incoming data before comma alignment or decoding. This function can be used to test
the signal integrity of the channel.
X-Ref Target - Figure 4-20
Polarity
SIPO
Inversion
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
defines the RX oversampling ports.
Dir Clock Domain
In RXUSRCLK2
Out RXUSRCLK2
defines the RX oversampling attributes.
Type
25-bit Hex This 25-bit attribute allows the operation of the CDR to be
adjusted. In normal operation, set the attribute PMA_RX_CFG to
the default value generated by the wizard. In oversampling mode,
PMA_RX_CFG is set to 25'h0F44000.
Boolean This attribute enables receiver oversampling when TRUE and
when 5X oversampling is On.
Integer RXPLL_DIVSEL_OUT must be set to 1 when using oversampling
mode.
PRBS-7 Pattern Checker
PRBS-15 Pattern Checker
PRBS-23 Pattern Checker
PRBS-31 Pattern Checker
Figure 4-20: RX Pattern Generator Block
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Description
When this port is High, the 5X oversampler in the PCS
continually adjusts its sample point. When this port is Low,
it samples only at the point that was active before the port
went Low.
When this port is High, the FIFO in the oversampling circuit
has either overflowed or underflowed. The PCS must be
reset to resume proper operation.
Description
Error
Error Counter
(16 bits)
RX Pattern Checker
RX_PRBS_ERR_CNT
RXPRBSERR
RXENPRBSTST
RXDATA
UG366_c4_18_120809
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