Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

Chapter 2: Shared Transceiver Features

Ports and Attributes

Table 2-18
Table 2-18: DRP Ports
Port Dir
DADDR[7:0] In
DCLK In
DEN In
DI[15:0] In
DRDY Out
DRPDO[15:0] Out
DWE In
There are no DRP attributes.
Note:
set by writing to the DRP of the first transceiver in the Quad. The first transceiver in the Quad has the
lowest Y coordinates. Refer to
numbering.
www.BDTIC.com/XILINX
126
defines the DRP ports.
Clock Domain
DCLK DRP address bus.
N/A DRP interface clock.
DCLK DRP enable signal.
0: No read or write operation performed.
1: Enables a read or write operation.
DCLK Data bus for writing configuration data from the FPGA logic resources to
the GTX transceiver.
DCLK Indicates operation is complete for write operations and data is valid for
read operations.
DCLK Data bus for reading configuration data from the GTX transceiver to the
FPGA logic resources.
DCLK DRP write enable.
0: Read operation when DEN is 1.
1: Write operation when DEN is 1.
Attributes that have an impact on the entire Quad (the cluster of four GTX transceivers) are
Implementation, page 41
www.xilinx.com
Description
for details on transceiver placement and
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011