Sim_Receiver_Detect_Pass; Sim_Rxrefclk_Source; Sim_Txrefclk_Source - Xilinx Virtex-6 FPGA User Manual

Chapter 1: Transceiver and Tool Overview
If TXOUTCLK or RXRECCLK is used to generate clocks in the design, these clocks
occasionally flatline while the GTX transceiver is locking. If an MMCM is used to divide
TXOUTCLK or RXRECCLK, the final output clock is not ready until both the GTX
transceiver and the MMCM have locked.
required before a stable source from TXOUTCLK or RXRECCLK is available in simulation,
including the time required for any MMCMs used.
If the MMCM is not used, the term can be removed from the lock time equation.

SIM_RECEIVER_DETECT_PASS

The GTX transceiver includes a TXDETECTRX feature that allows the transmitter to detect
whether its serial ports are currently connected to a receiver by measuring rise time on the
TXP/TXN differential pin pair (see
page
The GTXE1 SecureIP model includes an attribute for simulating TXDETECTRX called
SIM_RECEIVER_DETECT_PASS. This attribute allows TXDETECTRX to be simulated for
the GTX transceiver without modeling the measurement of rise time on the TXP/TXN
differential pin pair.
By default, SIM_RECEIVER_DETECT_PASS is set to FALSE. When FALSE, the attribute
models a disconnected receiver and TXDETECTRX operations indicate a receiver is
disconnected. To model a connected receiver, SIM_RECEIVER_DETECT_PASS for the
transceiver is set to TRUE.

SIM_RXREFCLK_SOURCE

The GTXE1 SecureIP model includes an attribute to select the reference clock source used
to drive the RX PMA PLL in simulation called SIM_RXREFCLK_SOURCE. This attribute is
to be used in designs where the RX PMA PLL's clock input is always driven by the same
reference clock source.
Reference clock sources include the dedicated clock pins of the Quad that the transceiver
belongs to, the north-running reference clocks, the south-running reference clocks, and a
clock from the FPGA logic.
For multi-rate designs requiring the reference clock source driving the RX PMA PLL to be
changed on the fly, the RXPLLREFSELDY port is used to dynamically select the reference
clock source instead.

SIM_TXREFCLK_SOURCE

The GTXE1 SecureIP model includes an attribute to select the reference clock source used to
drive the TX PMA PLL in simulation called SIM_TXREFCLK_SOURCE. This attribute is to be
used in designs where the TX PMA PLL's clock input is always driven by the same reference clock
source.
Reference clock sources include the dedicated clock pins of the Quad that the transceiver
belongs to, the north-running reference clocks, the south-running reference clocks, and a
clock from the FPGA logic.
For multi-rate designs requiring the reference clock source driving the TX PMA PLL to be
changed on the fly, the TXPLLREFSELDY port is used to dynamically select the reference
clock source instead.
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40

t t
USRCLKstable GTXRESETsequence
179).
Table 1-2
Table 1-2
www.xilinx.com
Equation 1-1 provides an estimate of the time
t
+
locktimeMMCM
TX Receiver Detect Support for PCI Express Designs,
shows the possible settings for this attribute.
shows the possible settings for this attribute.
Virtex-6 FPGA GTX Transceivers User Guide
Equation 1-1
UG366 (v2.5) January 17, 2011