Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

X-Ref Target - Figure 4-35
Clock correction should be used whenever there is a frequency difference between XCLK
and RXUSRCLK. It can be avoided by using the same frequency source for TX and RX, or
by using the recovered clock to drive RXUSRCLK. The
details about the steps required if clock correction is not used.

Ports and Attributes

Table 4-46
Table 4-46: RX Clock Correction Ports
Port
RXBUFRESET
RXBUFSTATUS[2:0]
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Read
RXUSRCLK
Read
Repeatable Sequence
defines the RX clock correction ports.
Dir Clock Domain
In Async Resets the RX elastic buffer logic and re-initializes the RX elastic
buffer.
Out RXUSRCLK2 Indicates the status of the RX elastic buffer as follows:
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"Nominal" Condition: Buffer Half Full
Read
Repeatable Sequence
Buffer Less Than Half Full (Emptying)
Buffer More Than Half Full (Filling Up)
Figure 4-35: Clock Correction
Description
000: Nominal condition
001: Number of bytes in the buffer are less than
CLK_COR_MIN_LAT
010: Number of bytes in the buffer are greater than
CLK_COR_MAX_LAT
101: RX elastic buffer underflow
110: RX elastic buffer overflow
RX Clock Correction
Write
XCLK
Write
Write
UG366_c4_32_051509
RX Elastic Buffer section has more
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