Power Down - Xilinx Virtex UltraScale+ FPGAs User Manual

Power Down

The GTM transceiver offers different levels of power control. Each channel in each direction can
be powered down separately. The PLLPD port directly affects the LCPLL.
Ports and Attributes
The following table defines the power-down ports.
Table 20: Power-Down Ports
Port
PLLPD
The following table defines the power-down attributes.
Table 21: Power-Down Attributes
Attribute
CH[0/1]_TX_ANA_CFG0
Bit Name
TXPWRDN_B
RST_CFG
Bit Name
RX_PDB_CH0
RX_PDB_CH1
PLL Power Down
To activate the LCPLL power-down mode, the active-Low PLLPD signal is asserted. When PLLPD
is deasserted, the LCPLL is powered down. As a result, all clocks derived from the PLL are
stopped. Recovery from this power state is indicated by the PLL lock signal PLLLOCK.
TX and RX Power Down
TX and RX power control signals can be used independently. Only two power states are
supported, as shown in the following table. Powering up/down multiple lanes in a Dual or
multiple Duals affects the power supply regulation circuit (see
Multiple Lanes).
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Dir Clock Domain
In Async
Type
16-bit
Address
[1:0]
16-bit
Address
[2]
[3]
Chapter 2: Shared Features
Description
This active-Low signal powers down the LCPLL.
Description
Reserved.
Description
Powers down channel TX:
2'b00: Power down.
2'b11: Power up.
Reserved.
Description
This active-Low signal powers down channel 0 RX.
This active-Low signal powers down channel 1 RX.
Power Up/Down and Reset on
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