Txoutclk Driving More Than One Gtx Tx In 4-Byte Mode (Multiple Lanes) - Xilinx Virtex-6 FPGA User Manual

Chapter 3: Transmitter
X-Ref Target - Figure 3-5
For details about placement constraints and restrictions on clocking resources (MMCM,
BUFGCTRL, IBUFDS_GTXE1, BUFG, etc.), refer to the Virtex-6 FPGA Clocking Resources
User Guide.
TXOUTCLK Driving More Than One GTX TX in 4-Byte Mode (Multiple
Lanes)
In
frequency must be correct for all the GTX transceivers, and they must share the same
reference clock. In 4-byte mode (TX_DATA_WIDTH = 32 or 40), the GEN_TXUSRCLK
attribute is set to "FALSE", and TXOUTCLK is used as the reference clock for the MMCM.
TXOUTCLK is used to drive the CLKIN signal of the MMCM to derive two positive-edge
aligned CLKOUT0 and CLKOUT1 signals, where the CLKOUT1 frequency is equal to the
CLKOUT0 frequency divided by 2. The user can use either TXPLLKDET or RXPLLLKDET
as a reset signal for the MMCM. If the TX PLL for each transceiver is not used and is
derived from the RX PLL, the active-High RXPLLLKDET signal should be used to deassert
the RST signal of the MMCM. TXOUTCLK can be used to drive CLKIN directly without
using the BUFG resources. In the use models where TX Buffer is bypassed, TXOUTCLK
must drive CLKIN directly. This requires the MMCM to be placed in the same clock region
as the driving GTX.
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134
TXPLLLKDET/
RXPLLLKDET
TXOUTCLK
GTX
TXUSRCLK
Transceiver
TXUSRCLK2
TXDATA (16 or 20 bits)
TXUSRCLK
GTX
TXUSRCLK2
Transceiver
TXDATA (16 or 20 bits)
Figure 3-5: TXOUTCLK Drives TXUSRCLK2 (2-Byte Mode)
Figure 3-6, TXOUTCLK is used to drive multiple GTX user clocks. In this case, the
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BUFG or BUFR
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Design
in
FPGA
UG366_c3_24_122810