Gtx Transceiver Power Connections - Xilinx Virtex-6 FPGA User Manual

Chapter 5: Board Design Guidelines
layers above and below the power planes. Because of their low impedance, power planes
are often prime candidates for providing return current paths for signals routed above or
below them, even if the path is not intended. The ground planes also provide a means to
connect the ground pins in the GTX transceiver region of the Virtex-6 FPGA.

GTX Transceiver Power Connections

Connections between the GTX power pins and the power distribution network are critical
to the overall transceiver performance. The interface between the power distribution
network and FPGA must be low impedance and low noise. The maximum noise allowed
on the GTX power supplies at the FPGA is 10 mV
As mentioned in
islands.
Figure 5-12
Virtex-6 package pinout. The power islands do not protrude into the SelectIO interface
region of the FPGA.
X-Ref Target - Figure 5-12
Figure 5-13
the Virtex-6 FPGA and how to avoid exposure to the SelectIO interface region of the
Virtex-6 FPGA BGA pin field. It also shows how filter capacitors discussed in
Supply Decoupling Capacitors, page 286
adequate noise filtering.
www.BDTIC.com/XILINX
288
Board Stackup, the GTX transceiver power can be supplied by power
shows the orientation of the power islands to the GTX transceiver region of the
GND Plane
1.0V MGTAVCC Power Island
1.2V MGTAVTT Power Island
GND Plane
Figure 5-12: GTX Power Supply Islands
shows how the power islands are oriented under the GTX transceiver region of
www.xilinx.com
from 10 kHz to 80 MHz.
PP
Transceiver BGA Region
can be oriented on the power planes to provide
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
UG366_c5_12_051509
Power