Power Supply Distribution Network; Staged Decoupling; Power Supply Decoupling Capacitors; Printed Circuit Board Design - Xilinx Virtex-6 FPGA User Manual

Chapter 5: Board Design Guidelines

Power Supply Distribution Network

Staged Decoupling

Die
There is decoupling capacitance on the die to filter the highest frequency noise components
on the power supplies. The internal on-die circuits are the source for this very high
frequency noise.
Package
Additional decoupling is in the Virtex-6 FPGA packages. Decoupling capacitors in the
package provide attenuation for noise in the package power plane, thereby reducing the
interaction between Quads. These capacitors in the package also help to maintain a low-
impedance, high-frequency path between the power supply (MGTAVCC or MGTAVTT)
and ground.
Printed Circuit Board
Because the impedance between the power planes and ground has been kept low on the
die and in the package, the requirement for decoupling on the PCB is more relaxed.
Because the power supplies of the Quads are common and decoupled in the package,
filtering is not necessary on the PCB to isolate the Quad power supply connections.
Decoupling capacitors provide two basic functions:
1.
2.

Power Supply Decoupling Capacitors

For the GTX transceiver analog power supplies, the primary purpose of decoupling
capacitors is to reduce the noise amplitude from the power supply source and other
circuits on the PCB. The suggested filtering for the MGTAVCC and MGTAVTT power
supplies is:
•
•
•

Printed Circuit Board Design

Optimal performance from the GTX transceivers requires careful consideration in the
design of the PCB. The areas of PCB design that must be considered are board stackup,
component placement, and signal routing. The PCB design includes:
•
•
•
•
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They help to isolate one circuit from another so that noise induced on the power
supply by one circuit does not induce noise on the power supply of another circuit. In
this case, the concern is noise coupling between Quads in the same FPGA.
They provide isolation between the power supply source and the load circuit.
One 0.22 µF, size 0402, ceramic capacitor per power supply pin
One 4.7 µF, size 0402, ceramic capacitor per two Quads
One 330 µF bulk capacitor for each power supply
Power distribution network for MGTAVTT and MGTAVCC
Data lines for the receiver and transmitter
Reference clock connections between the source oscillator and the GTX reference clock
input
Termination calibration resistor (see
page 274)
www.xilinx.com
Termination Resistor Calibration Circuit,
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011