Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

The GTX transceiver supports beaconing as described in the PHY Interface for the PCI
Express (PIPE) Specification. The format of the beacon sequence is controlled by the FPGA
logic.

Ports and Attributes

Table 3-34
Table 3-34: TX OOB Ports
Port
COMFINISH
TXCOMINIT
TXCOMSAS
TXCOMWAKE
TXELECIDLE
TXPOWERDOWN[1:0]
Table 3-35
Table 3-35: TX OOB Attributes
Attribute
COM_BURST_VAL
TXPLL_SATA
The GTX transceiver supports four signaling modes: three for SATA/SAS operations and
one for PCI Express operations. The use of these mechanisms is mutually exclusive.
www.BDTIC.com/XILINX
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
defines the TX OOB ports.
Direction Clock Domain
Out TXUSRCLK2
In TXUSRCLK2
In TXUSRCLK2
In TXUSRCLK2
In TXUSRCLK2
In TXUSRCLK2
defines the TX OOB attributes.
Type
4-bit Binary This attribute determines the number of bursts in a COM
sequence.
2-bit Binary Reserved. Use only recommended values from the
Virtex-6 FPGA GTX Transceiver Wizard.
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Description
This output indicates completion of transmission of the last
SAS or SATA TXCOM sequence.
This input initiates the transmission of the TXCOMINIT
sequence.
This input initiates the transmission of the TXCOMSAS
sequence.
This input initiates the transmission of the TXCOMWAKE
sequence.
When in the PCIe P2 power state, this signal controls
whether an electrical idle or a beacon indication is driven
onto the TX pair. When in SATA mode, keep TXELECIDLE
High for generating SATA/SAS OOB COM signaling.
This input powers down the TX lanes. It is primarily used for
PCIe designs. Use TXPOWERDOWN = 00 for operating
SATA OOB signaling.
Description
TX Out-of-Band Signaling
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