Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

The RX PLL provides a base clock to the phase interpolator. The phase interpolator in turn
produces fine, evenly spaced sampling phases to allow the CDR state machine to have fine
phase control. The CDR state machine can track incoming data stream that can have a
frequency offset, usually no more than ±1000 PPM, from the local PLL reference clock.
Methods for detecting CDR lock include:
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Ports and Attributes

Table 4-21
Table 4-21: RX CDR Ports
Port Dir
RXCDRRESET In
RXRATE[1:0] In
Table 4-22
Table 4-22: RX CDR Attributes
Attribute
CDR_PH_ADJ_TIME
PMA_CDR_SCAN
PMA_RX_CFG
RX_EN_IDLE_HOLD_CDR
RX_EN_IDLE_RESET_FR
RX_EN_IDLE_RESET_PH
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Finding known data in the incoming data stream (for example, commas or A1/A2
framing characters). In general, several consecutive known data patterns must be
received without error to indicate a CDR lock.
Using the LOS state machine (see
incoming data is 8B/10B encoded and the CDR is locked, the LOS state machine
moves to the SYNC_ACQUIRED state and stays there.
defines the RX CDR ports.
Clock Domain
Async Active-High CDR reset that resets the CDR logic and the RX part of the
PCS for this channel. This signal needs to be asserted whenever the
frequency of the RX PLL changes.
RXUSRCLK2 This port and RX PLL output divider attribute, RXPLL_DIVSEL_OUT,
defines the line rate for the receiver based on the RX PLL frequency. Refer
to RX Fabric Clock Output Control, page 207
defines the RX CDR attributes.
Type
5-bit Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Binary Transceiver Wizard.
This attribute defines the delay after deassertion of the CDR phase reset
before the optional reset sequence of PCI Express operation is complete
during electrical idle.
27-bit Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Hex Transceiver Wizard.
25-bit Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Hex Transceiver Wizard. For lock-to-reference operation, set PMA_RX_CFG to
25'h05CE000.
Boolean When set to TRUE, it enables the CDR to hold its internal states during an
optional reset sequence of an electrical idle state as used in PCI Express
operation.
Boolean When set to TRUE, it enables automatic reset of CDR frequency during an
optional reset sequence of an electrical idle state as used in PCI Express
operation.
Boolean When set to TRUE, it enables automatic reset of CDR phase during an
optional reset sequence of an electrical idle state as used in PCI Express
operation.
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RX Loss-of-Sync State Machine, page
Description
Description
RX CDR
226). If
for more details.
205