Port And Attribute Summary - Xilinx Virtex-6 FPGA User Manual

This cluster of four GTX transceivers share two differential reference clock pin pairs and
clock routing.
clock sources and the routing.

Port and Attribute Summary

The ports and attributes are grouped in tables for each functionality group (e.g., reference
clock selection). If a port or attribute appears in multiple chapters, it is listed in the group
of its first appearance.
functionality group.
Note:
are present in the instantiation primitive or are listed in
Transceiver
Table 1-1: Port and Attribute Summary
Simulation
Clocking
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 2, Shared Transceiver
Table 1-1
Table 1-1 lists all the ports and attributes covered in this user guide. Some ports or attributes
but not in Table 1-1.
Port/Attribute
Attributes:
• SIM_GTXRESET_SPEEDUP
• SIM_RECEIVER_DETECT_PASS
• SIM_RXREFCLK_SOURCE
• SIM_TX_ELEC_IDLE_LEVEL
• SIM_TXREFCLK_SOURCE
• SIM_VERSION
Ports:
• GREFCLKRX
• GREFCLKTX
• MGTREFCLKRX[1:0]
• MGTREFCLKTX[1:0]
• NORTHREFCLKRX[1:0]
• NORTHREFCLKTX[1:0]
• PERFCLKRX
• PERFCLKTX
• RXPLLREFSELDY[2:0]
• SOUTHREFCLKRX[1:0]
• SOUTHREFCLKTX[1:0]
• TXPLLREFSELDY[2:0]
Attributes:
• PMA_CAS_CLK_EN
• SIM_RXREFCLK_SOURCE[2:0]
• SIM_TXREFCLK_SOURCE[2:0]
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Features, discusses details about reference
summarizes the ports and attributes according to
Appendix B, DRP Address Map of the GTX
Port and Attribute Summary
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