Tx Overview - Xilinx Virtex-6 FPGA User Manual

Transmitter

TX Overview

This chapter shows how to configure and use each of the functional blocks inside the GTX
transmitter (TX). Each GTX transceiver includes an independent transmitter, which
consists of a PCS and a PMA.
Parallel data flows from the FPGA into the FPGA TX interface, through the PCS and PMA,
and then out the TX driver as high-speed serial data.
X-Ref Target - Figure 3-1
TX TX
TX
OOB Pre/
Driver
and Post
PCIe emp
PISO
PMA
PLL
Divider
TX-PMA
The key elements of the GTX TX are:
1.
2.
3.
4.
5.
6.
7.
www.BDTIC.com/XILINX
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Polarity
To RX Parallel
Data (Near-End
PCS Loopback)
Figure 3-1: GTX TX Block Diagram
FPGA TX Interface, page 128
TX Initialization, page 136
TX 8B/10B Encoder, page 143
TX Gearbox, page 146
TX Buffer, page 153
TX Buffer Bypass, page 155
TX Pattern Generator, page 162
www.xilinx.com
Figure 3-1 shows the functional blocks of the transmitter.
Pattern
Generator
Phase
Adjust
FIFO &
Over-
sampling
PCIe
Beacon
SATA
OOB
From RX Parallel Data
(Far-End PMA Loopback)
Chapter 3
TX
Gearbox
TX PIPE
Control
FPGA
TX
Interface
8B/
10B
TX-PCS
From RX Parallel Data
(Far-End PCS Loopback)
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