Xilinx Virtex-6 FPGA User Manual page 5

Date Version
01/19/10 2.1
02/23/10 2.2
www.BDTIC.com/XILINX
UG366 (v2.5) January 17, 2011
Updated width of TXBUFSTATUS port in
of SIM_GTXRESET_SPEEDUP in
Figure 1-9.
Added new section Reference Clock Input Structure, page
Figure 2-5, Figure 2-6, and
Description. Removed Line Rate Range column and added -1 Line Rate Range and -2/-3 Line
Rate Range columns to Table
divider setting after Table
columns from Table 2-10. Removed Power Down Transition Times section. Updated
Description column of Table
Moved Ports and Attributes, page 130
page 131. Updated Using TXOUTCLK to Drive the GTX TX, page
asynchronous GTXTXRESET pulse width in
Pulse, page 139. Added TXDLYALIGNMONENB and updated descriptions of
TXDLYALIGNRESET, TXOUTCLK, and TXPMASETPHASE to
and 6 in Using the TX Phase-Alignment Circuit to Bypass the Buffer, page
Oversampling, page 166. In
TX_OVERSAMPLE_MODE, and added TXPLL_DIVSEL_OUT. Added note 5 to
Updated line rate ranges in
and added a note after the figure. Replaced TXPREEMPHASIS with TXPOSTEMPHASIS in
description of TXDEEMPH in
for Table 3-31. Replaced TXPREEMPHASIS with TXPOSTEMPHASIS in descriptions of
TX_DEEMPH_0/1 in Table
PCIe Mode, page 178 and
Added note after Figure 4-2
OOBDETECT_THRESHOLD_0/1 to and updated description of SATA_IDLE_VAL in
Table 4-10. Updated descriptions of DFETAPOVRD and DFEDLYOVRD ports after
Figure 4-12. Updated descriptions of DFECLKDLYADJ, DFECLKDLYADJMON, and
DFEDLYOVRD in Table 4-11. Updated descriptions of DFE_CAL_TIME, DFE_CFG, and
RX_EN_IDLE_HOLD_DFE attributes in
section as RX Fabric Clock Output Control, page
and added note 4 to Figure
Analysis, page 210. Added DFEEYEDACMON port to
INTDATAWIDTH with RX_DATA_WIDTH in and added note to
RXOVERSAMPLER to RXOVERSAMPLEERR in
RX_OVERSAMPLE_MODE in and added RXPLL_DIVSEL_OUT to
order of the SIPO and Polarity Inversion blocks in
RX_PRBS_ERR_CNT and RXPRBSERR_LOOPBACK attributes in
GTXRESET with GTXRXRESET in
MCOMMA_ALIGN to PCOMMA_DETECT and MCOMMA_DETECT, respectively, in
Alignment Status Signals, page 219
restrictions on RX buffer bypass operation. Updated descriptions of
CHAN_BOND_1/2_MAX_SKEW a nd CHAN_BOND_SEQ_LEN attribute in
Added guideline for asynchronous GTXTXRESET pulse width in
to GTXRXRESET Pulse, page
MGTAVCC and VCCINT in
In Table B-1, changed attribute encoding 3 in attribute bits 1:0 of DADDRs 7h, 12h, and 13h
to Reserved.
Updated descriptions of RXDLYALIGNOVERRIDE in
RX_DLYALIGN_OVRDSETTING in
Circuit to Bypass the Buffer, page
Figure 4-33.
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Revision
Table 1-1. Updated
Table 1-2. Added GTXE1_X0Y1 location for LX75T to
Figure 2-7. Updated PLL nominal operation range in
2-6. Added note after Figure
2-7. Updated entries in and removed REFCLK Max and Min
2-10.
before Using TXOUTCLK to Drive the GTX TX,
GTX TX Reset in Response to GTXTXRESET
Table 3-26, removed PMA_RX_CFG, updated description of
Table 3-28. Changed IBUFDS to IBUFDS_GTXE1 in
Table 3-31. Changed PCI Express version from 3.0 to 2.0 in note
3-32. Replaced TXPREEMPHASIS with TXPOSTEMPHASIS in
Customizable User Presets, page
and Table 4-3. Updated
Table 4-12. Renamed RX Clock Divider Control
207. Updated MGTREFCLKFAB[1] bit in
4-15. Updated line rate ranges in
Table
Figure
Use Models, page
and Table 4-34. Updated
263. Added description of power supply regulators for
Overview, page 283.
Table 4-41. Updated
235, including Note 2 in
Virtex-6 FPGA GTX Transceivers User Guide
Figure 1-4. Updated description
101. Added note after
2-9. Added description of N1
131. Added guideline for
Table 3-18. Updated steps 1d
158. Updated
178.
Table 4-5 and Table 4-7. Added
Table 4-23. Updated
Table 4-26. Replaced
Figure 4-19. Changed
4-29. Updated description of
Table 4-30. Swapped the
4-20. Updated descriptions of
Table 4-32. Replaced
216. Changed PCOMMA_ALIGN and
RX Buffer Bypass, page 231
GTX RX Reset in Response
Table 4-40 and
Using the RX Phase Alignment
Notes for Figure 4-32.. Updated
Figure 2-4,
Functional
TX
Figure 3-28.
Figure 3-29
RX Margin
with
Table 4-49.