Tx Buffer; Functional Description - Xilinx Virtex-6 FPGA User Manual

TX Buffer

Functional Description

The GTX TX datapath has two internal parallel clock domains used in the PCS: the PMA
parallel clock domain (XCLK) and the TXUSRCLK domain. To transmit data, the XCLK
rate must match the TXUSRCLK rate, and all phase differences between the two domains
must be resolved.
X-Ref Target - Figure 3-20
TX Serial Clock
TX
TX
TX
OOB Pre/
PISO
Driver
Post
and
PCIe Emp
PMA
PLL
Divider
TX-PMA
The GTX transmitter includes a TX buffer and a TX phase-alignment circuit to resolve
phase differences between the PMACLK and TXUSRCLK domains. All TX datapaths must
use these circuits.
Table 3-15: Buffering vs. Phase Alignment
Ease of Use The TX buffer is used when
possible. It is robust and easy
to operate.
Latency If low latency is critical, the
TX buffer must be bypassed.
TX Lane-to-
Lane Deskew
Oversampling The TX buffer is required for
oversampling.
www.BDTIC.com/XILINX
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Figure 3-20
PMA Parallel Clock
(XCLK)
PCIe
Beacon
SATA
Polarity
OOB
TX-PCS
To RX Parallel
Data (Near-End
PCS Loopback)
Figure 3-20: TX Clock Domains
Table 3-15
TX Buffer
Phase alignment requires extra logic and additional constraints on
clock sources. TXOUTCLK cannot be used unless the
TXOUTCLK_CTRL attribute is set to "TXPLLREFCLK_DIV1" or
"TXPLLREFCLK_DIV2".
Phase alignment uses fewer registers in the datapath.
The phase-alignment circuit can be used to reduce the skew between
separate GTX transceivers. All GTX transceivers involved must use
the same line rate.
www.xilinx.com
shows the XCLK and TXUSRCLK domains.
PCS Parallel Clock
(TXUSRCLK)
TX
Gearbox
Pattern
Generator
Phase
Adjust
FIFO &
Over-
sampling
From RX
Parallel Data
(Far-End PMA
Loopback)
shows trade-offs between buffering and phase alignment.
TX Phase Alignment
TX Buffer
FPGA
Parallel Clock
(TXUSRCLK2)
TX PIPE
CONTROL
8B
/
10B
From RX
Parallel Data
(Far-End PCS
Loopback)
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