Generic Power-Down Capabilities - Xilinx Virtex-6 FPGA User Manual

Gtx transceivers
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Table 2-12: Power-Down Attributes
Attribute
BGTEST_CFG
BIAS_CFG
PMA_TX_CFG
POWER_SAVE
TRANS_TIME_FROM_P2
TRANS_TIME_NON_P2
TRANS_TIME_RATE
TRANS_TIME_TO_P2

Generic Power-Down Capabilities

The GTX transceiver provides several power-down features that can be used in a wide
variety of applications.
www.BDTIC.com/XILINX
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Type
2-bit
Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Hex
Transceiver Wizard.
17-bit
Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Hex
Transceiver Wizard.
20-bit
Reserved. Use only recommended values from the Virtex-6 FPGA GTX
Hex
Transceiver Wizard.
10-bit
POWER_SAVE[4]:
Binary
Mux select for the TXOUTCLK output clock. Must be tied to 1'b1.
1'b0: Use the TX Delay Aligner
1'b1: Bypass the TX Delay Aligner
POWER_SAVE[5]:
Mux select for the RXRECCLK output clock. Must be tied to 1'b1 when RX
buffer is used (RX_BUFFER_USE = TRUE). When RX buffer is bypassed, refer
to
Using the RX Phase Alignment Circuit to Bypass the Buffer, page
1'b0: Use the RX Delay Aligner
1'b1: Bypass the RX Delay Aligner
All other bits are reserved. Use recommended values from the Virtex-6 FPGA
GTX Transceiver Wizard.
12-bit
Counter settings for programmable transition time from P2 state for PCIe
Hex
operation. Use recommended values from the Virtex-6 FPGA GTX Transceiver
Wizard.
8-bit
Counter settings for programmable transition time to/from all states except P2
Hex
for PCIe operation. Use recommended values from the Virtex-6 FPGA GTX
Transceiver Wizard.
8-bit
Counter settings for programmable transition time when rate is changed using
Hex
RATE pins for all protocols including the PCIe protocol (Gen2/Gen1 data
rates). Set to the maximum value for non PCIe modes. Use recommended
values from the Virtex-6 FPGA GTX Transceiver Wizard.
10-bit
Counter settings for programmable transition time to the P2 state for PCIe
Hex
operation. Use recommended values from the Virtex-6 FPGA GTX Transceiver
Wizard.
Table 2-13
www.xilinx.com
Description
summarizes these capabilities.
Power Down
235.
121

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