Using The Rx Elastic Buffer For Channel Bonding Or Clock Correction; Rx Clock Correction; Functional Description - Xilinx Virtex-6 FPGA User Manual

Chapter 4: Receiver
Table 4-44: RX Elastic Buffer Attributes (Cont'd)
Attribute
RX_IDLE_LO_CNT
RX_XCLK_SEL

Using the RX Elastic Buffer for Channel Bonding or Clock Correction

The RX elastic buffer is also used for clock correction (see
channel bonding (see
where PMACLK and RXUSRCLK are not frequency matched.
clock configurations and shows whether they require clock correction.
Table 4-45: Common Clock Configurations
To use the RX elastic buffer for channel bonding or clock correction:
•
•
•

RX Clock Correction

Functional Description

The RX elastic buffer has an additional benefit: it can tolerate frequency differences
between the XCLK and RXUSRCLK domains by performing clock correction. Clock
correction actively prevents the RX elastic buffer from getting too full or too empty by
deleting or replicating special idle characters in the data stream.
Figure 4-35
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240
Type
4-bit Determines count value after which a deassertion of reset due to
Binary RX_EN_IDLE_RESET_BUF is triggered after valid data once again present on
the RXP/RXN lines. Use the Virtex-6 FPGA GTX Transceiver Wizard default.
String Selects the clock used to drive the RX parallel clock domain (XCLK).
"RXREC": (default) XCLK domain driven by recovered clock from CDR.
When RX_OVERSAMPLE_MODE is TRUE, the recovered clock is sourced
from the oversampling block.
"RXUSR": RXUSRCLK port drives RX parallel clock domain. Use this
mode when bypassing the RX elastic buffer.
RX Channel Bonding, page
Synchronous System (both sides use same physical oscillator for
REFCLK)
Separate Reference Clocks, RX uses recovered clock
Separate Reference Clocks, RX uses local clock
Set RX_BUFFER_USE to TRUE.
Reset the buffer whenever RXBUFSTATUS indicates an overflow or an underflow.
The buffer can be reset using GTXRXRESET, RXRESET, or RXBUFRESET (see
Initialization, page 261).
shows a conceptual view of clock correction.
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Description
RX Clock Correction) and
247). Clock correction is used in cases
Table 4-45
Needs Clock Correction?
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
lists common
No
No
Yes
RX