Power Down; Functional Description; Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

Chapter 2: Shared Transceiver Features

Power Down

Functional Description

The GTX transceiver supports a range of power-down modes. These modes support both
generic power management capabilities as well as those defined in the PCI Express and
SATA standards.
The GTX transceiver offers different levels of power control. Each channel in each direction
can be powered down separately using TXPOWERDOWN and RXPOWERDOWN. The
TXPLLPOWERDOWN and RXPLLPOWERDOWN port directly affects the shared.

Ports and Attributes

Table 2-11
Table 2-11: Power-Down Ports
Port
RXPLLPOWERDOWN
RXPOWERDOWN[1:0]
TXPDOWNASYNCH
TXPLLPOWERDOWN
TXPOWERDOWN[1:0]
Table 2-12
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120
defines the power-down ports.
Dir Clock Domain
In Async
In Async
In Async
In Async
In TXUSRCLK2
(TXPDOWNASYNCH
makes this pin
asynchronous)
defines the power-down attributes.
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Description
Input to power down the RX PLL.
Powers down the RX lane according to the PCIe® protocol
encoding.
00: P0 (normal operation)
01: P0s (low recovery time power down)
10: P1 (longer recovery time)
11: P2 (lowest power state)
Determines whether TXELECIDLE and TXPOWERDOWN
should be treated as synchronous or asynchronous signals.
0: Sets TXELECIDLE and TXPOWERDOWN to
synchronous mode.
1: Sets TXELECIDLE and TXPOWERDOWN to
asynchronous mode.
Input to power down the TX PLL.
Powers down the TX lane according to the PCIe protocol
encoding.
00: P0 (normal operation)
01: P0s (low recovery time power down)
10: P1 (longer recovery time; Receiver Detection still on)
11: P2 (lowest power state)
Attributes can control the transition times between these
power-down states.
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011