Rx_Dlyalign_Ctrinc; Rx_Dlyalign_Lpfinc; Rx_Dlyalign_Ovrdsetting - Xilinx Virtex-6 FPGA User Manual

Appendix B: DRP Address Map of the GTX Transceiver
Table B-1: Attributes DRP Address Map (Cont'd)
DADDR DRP Bits R/W
15:8
4Ch 7:4
3:0
R/W
15:8
7:4
4Dh
3:0
15:0 R/W
4Eh
15:0 R/W
4Fh
Notes:
1. The DRP has the same binary encoding value as the attribute encoding value.
Table B-2: Status Registers DRP Address Map
DADDR
DRP Bits R/W
(2)
15:0 R
82h
Notes:
1. The DRP has the same binary encoding value as the attribute encoding value.
2. The receiver has to be operational for this DRP register to take effect.
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314
Attribute Name
TX_DLYALIGN_OVRDSETTING
TX_DLYALIGN_LPFINC
TX_DLYALIGN_CTRINC

RX_DLYALIGN_OVRDSETTING

RX_DLYALIGN_LPFINC

RX_DLYALIGN_CTRINC

Reserved
Reserved
Register Name
RX_PRBS_ERR_CNT
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Attribute Bits Attribute Encoding
7:0 0-255
3:0 0-15
3:0 0-15
7:0 0-255
3:0 0-15
3:0 0-15
15:0
15:0
Register Encoding
Register Bits
0-65535
15:0
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
DRP Binary
Encoding
(1)
1
(1)
1
(1)
1
(1)
1
(1)
1
(1)
1
DRP Binary
Encoding
(1)
1