Tx Out-Of-Band Signaling; Functional Description - Xilinx Virtex-6 FPGA User Manual

Chapter 3: Transmitter
Table 3-33: TX Receiver Detect Support Ports (Cont'd)
Port
RXPOWERDOWN[1:0]
TXPOWERDOWN[1:0]
RXSTATUS[2:0]
TXDETECTRX
There are no TX receiver detect support attributes.

TX Out-of-Band Signaling

Functional Description

Each GTX transceiver provides support for generating the Out-of-Band (OOB) sequences
described in the Serial ATA (SATA), Serial Attach SCSI (SAS) specification, and beaconing
described in the PCI Express specification. GTX transceiver support for SATA/SAS OOB
signaling consists of the analog circuitry required to encode the OOB signal state and state
machines to format bursts of OOB signals for SATA/SAS COM sequences.
Each GTX transceiver also supports SATA and SAS auto-negotiation by allowing the
timing of the COM sequences to be changed based on the divider settings used for the TX
line rate.
Note:
at the current line rate operation.
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180
Dir Clock Domain
In Async
TXUSRCLK2
Out RXUSRCLK2
In TXUSRCLK2
The GTX transceiver transmits the ALIGNp primitive character within each OOB burst pulse
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Description
These inputs control the power state of the TX and RX
links. The encoding complies with the PCI Express
specification encoding. TX and RX can be powered
down separately.
00: P0 (normal operation)
01: P0s (low recovery time power down)
10: P1 (longer recovery time/Receiver detection still
on)
11: P2 (lowest power state)
PCI Only usage.
000: Receiver not present (when in receiver
detection sequence)/Received data OK (during
normal operation).
001: Reserved.
010: Reserved.
011: Receiver present (when in receiver detection
sequence).
100: 8B/10B decode error.
101: Elastic buffer overflow. Different than defined
in the PIPE specification.
110: Elastic buffer underflow. Different than defined
in the PIPE specification.
111: Receive disparity error.
This input activates the receive detection sequence. The
sequence ends when PHYSTATUS is asserted to
indicate that the results of the test are ready on
RXSTATUS.
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011