Use Modes: Reference Clock Termination; Reference Clock Selection; Functional Description - Xilinx Virtex-6 FPGA User Manual

Chapter 2: Shared Transceiver Features
Table 2-1: Reference Clock Input Ports (IBUFDS_GTXE1) (Cont'd)
Notes:
1. The O and ODIV2 outputs are not phase matched to each other.
Table 2-2
the reference clock input.
Table 2-2: Reference Clock Input Attributes (IBUFDS_GTXE1)

Use Modes: Reference Clock Termination

The reference clock input is to be externally AC coupled.
attribute settings required to achieve this.
Table 2-3: Port and Attribute Settings

Reference Clock Selection

Functional Description

GTX transceivers provide several available reference clock inputs. Clock selection and
availability changed slightly across the first three generations of Virtex® FPGA
transceivers. The Virtex-6 FPGA GTX transceiver significantly enhances reference clock
capabilities by adding dedicated clock routing and multiplexer resources. Architecturally,
the concept of a Quad (or Q), contains a grouping of four GTXE1 primitives, two dedicated
reference clock pin pairs, and dedicated reference clock routing. The term Quad in this
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102
Port Dir Clock Domain
O Out
(1)
ODIV2 Out
defines the attributes in the IBUFDS_GTXE1 software primitive that configure
Attribute
CLKRCV_TRST
CLKCM_CFG
Input Type
Ports
Attributes CLKRCV_TRST = TRUE
CLKCM_CFG = TRUE
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N/A This output drives the MGTREFCLKTX[0/1] and
MGTREFCLKRX[0/1] signals in the GTXE1
software primitive. Refer to
Selection, page 102
N/A This output is a divide-by-2 version of the O signal
that can drive the MGTREFCLKTX[0/1] and
MGTREFCLKRX[0/1] signals in the GTXE1
software primitive. Refer to
Selection, page 102
Type
Boolean RESTRICTED. This attribute switches in the
50 termination resistors into the signal path.
This attribute must always be set to TRUE.
Boolean RESTRICTED. This attribute switches in the
termination voltage for the 50 termination.
This attribute must always be set to TRUE.
Settings
CEB = 0
Virtex-6 FPGA GTX Transceivers User Guide
Description
Reference Clock
for more details.
Reference Clock
for more details.
Description
Table 2-3 shows the pin and
UG366 (v2.5) January 17, 2011