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Logic Analyzer
Specifications
Probes
State Mode
Timing Mode
The following specifications are the performance standards or limits against which
the HP 1652B/1653B logic analyzer is tested.
Minimum
Swing: 600 mV peak-to-peak.
Threshold Accuracy
olt;age Range
Accuraq
-2.ov to + 2.ov
t 150 mV
-9.9v
to
-2.N
& 300
mV
-I- 2.w
to
-I- 9.9v
t 300
mV
Clock Repetition
Rate: Single phase is 35 MHz maximum (25 MHz on the
HP 1653B). With time or state counting, minimum
time between states is 60 ns
(16.67 MHz).
Both mixed and demultiplexed
clocking use master-slave clock
timing. The master clock must follow the slave clock by at least 10 ns and precede
the next slave clock by ~50 ns.
Clock Pulse 'Width: ~10 ns at threshold.
Setup Time: Data must be present prior to the clock transition, > 10 ns.
Hold Time:
Data must be present after the rising clock transition, 0 ns.
Data must be present after the falling clock transition, 0 ns (HP 1653B). Data
must be present after the falling L clock transition, 0 ns (HP 1652B). Data must be
present after the falling J, K, M, and N clock transition, 1 ns (HP 1652B).
Minimum
Detectable Glitch: 5 a~ wide at the tlxe&&L
Logic Analyzer
The following operating characteristics are not specifications, but are typical
Operating
operating characteristics for the HP 1652B/1653B logic analyzer. These
Characteristics
characteristics are included as additional
information
for the user..
Probes
Input RC: 100 KQ t 2% shunted by approximately
8 pF at the probe tip.
Dynamic Range: & 10 volts about the threshold.
'ITL Threshold Preset: + 1.6 volts.
ECL Threshold Preset: -1.3 volts.
Threshold Range: -9.9 to + 9.9 volts in 0.1 volt increments.
Threshold Setting: Threshold levels may be defined for pods 1 and 2 individually
(HP 1653B). Threshold levels may be defined for pods 1,2, and 3 on an individual
basis and one threshold may be defined for pods 4 and 5 (HP 1652B).
HP 1652B/1653B
.
Service
Manual
General
Information
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