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Note
11 I lb
To ensure a consistent pattern of alternating Fs and OS, use the front-panel ROLL
field and knob to scroll through the State Listing.
7.
8 .
9 .
--
HP 16528116538
Service Manual
Connect the next clock to the test connector and repeat steps 4 and 6 for the
appropriate clock. Repeat these steps until the J, K, M, and N clocks have
been tested.
Remove the probe tip assembly from the logic analyzer probe cable and
attach it to the next logic analyzer probe cable to be tested. Take care not to
dislodge grabbers from the test connector.
Repeat steps 3,4,6, and 7 until
all pods have been tested (pods 1 through 5).
Disconnect the lower eight bits (bits 0 through 7) from the test connector.
Attach the upper eight bits (bits 8 through 15) to the test connector. Then
repeat steps 3,4,6,7,
and 8 until the upper bits of all pods have been tested
(pods 1 through 5).
Performance
Tests
3-17
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