HP 1652B Getting Started Manual page 597

6.
Press RUN. The
State Listing
is displayed and shows Fs for the channels
under test as in figure 3-10.
-
I
w] - IState Listing 1
tlarkers 1 Off ]
Label >
Base )
+oooo
+ooo 1
+0002
+0003
+0004
+ooos
WOO6
t+ooo7J
+oooe
+0009
+oOlO
MO11
HI012
+0013
MO14
+oOlS
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 3-10. State Listing for Data Test 1
I
Note !b
To ensure a consistent pattern of Fs in the listing, use the front-panel ROLL field
and knob to scroll through the
State Listing.
Performance Tests HP
16528/1653B
3-10 Service Manual
7. If you are testing the HP 1653B, connect the K clock of Pod 2 to the test
connector and repeat steps 4 and 6 for the falling edge of the K clock.
8. Remove the probe tip assembly from the logic analyzer probe cable and
attach it to the next logic analyzer probe cable to be tested. Take care not to
dislodge grabbers from the test connector. If you are testing the HP 1653B,
reassign the falling edge of the J clock.
9. Repeat steps 3,4,6 and 7 until all of the pods have been tested.
10. Disconnect the lower eight bits (bits 0 through 7) from the test connector and
attach the upper eight bits (bits 8 through 15) to the test connector.
11. Repeat steps 3,4,6,7 and 8 until the upper bits of all pods have been tested.