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2. Adjust the pulse generator for the output in figure 3-23.
WV---
3.2V
+
10NS
CLOCK
OUTPUT
B
.
----
I
Ov
I
I
'-120NS------d
I
I
I
I
----
3.2v
I
I
DATA,OUTPUT
A
----
I
Ov
40NS
-+
14-
60NS
-+I
I+-
20NS
0165ow14
Figure
3-23.
Waveform
for Data Test 5
Setting for
HP 8161A:
Parameter
Output A
Output B
Input Mode
Period (PER)
Width (WID)
Leading Edge (LEE)
Trailing Edge (TRE)
High Level HIL)
Low Level (LOL)
Delay (DEL)
Double Pulse (DBL)
Output Mode
Norm
120
ns
60
ns
1 ns
1 ns
3.2
V
ov
40
ns
B-B
ENABLE
m - m
IO ns
1
ns
1 ns
3.2
V
ov
0 ns
60
ns
ENABLE
3.
Assign the pod under test to
Analyzer 1 in
the
System Configuration as in
the previous figure 3-5.
4.
Set
up the
State Format Specification
as in figure 3-24. Assign the falling J
clock to the
Master Clock
and the rising J clock to the
Slave Clock.
Refer to
steps a through d after figure 3-24 if you are unfamiliar with menus.
State
Format
Speclflcatlon
l-laster
Clock
Slave
Clock
[
JJ.
]
1
Jt
1
Clock
Period
l(J
Activity
)
Label
Pal
Pod 1
-1
,,,,$$ss,,,,ss:3
15 . . . . 87 . , , . 0
. . . . .*a*,,.,**+*
Figure
3-34.
Format Specification
for Data Test 5
Performance
Tests
3-22
HP 1652B/1653B
Service Manual
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