Power Supply Assembly; Crt Monitor Assembly; Main Assembly; Oscilloscope Assembly - HP 1652B Getting Started Manual

Power Supply
Assembly
CRT Monitor
Assembly
Main Assembly
-
Central
Processing Unit
Pu)
Oscilloscope
Assembly
The switching power supply provides 120 W (200 W maximum) for the instrument.
The ac input, to the power supply is 115V or 230 V, -25% to + 15%. Maximum
input power is 350 VA maximum. The ac input frequency is 48 to 66 Hz.
All voltages necessary to operate the instrument are applied first to the Main
Assembly. Unfiltered voltages of + 15V, + 12V, -12V, + 5.15V, -5.2V, and + 3.5V
are supplied to the board where they are then filtered and distributed throughout
the main assembly board, oscilloscope board, and to the CRT Monitor Assembly.
Filtered voltages of approximately +5 V and + 12 V are routed through the Main
Assembly to the CRT Monitor Assembly. The + 5.15 V supply is adjustable on the
suPPlY=
The CRT Monitor Assembly consists of the sweep board circuitry, a g-inch white
phosphor CRT, and the CRT yoke. The assembly requires + 5 V and + 12 V from
the power supply via the Main Assembly.
The non-interlacing raster display is controlled by the CPU portion of the Main
Assembly. System control provides synchronization and pixel information.
The Main Assembly contains the logic analyzer acquisition system and system
control circuitry. It also provides interfaces for the Power Supply Assembly, CRT
Monitor Assembly, keyboard, RS-232C, and HP-IB. The input to the Main
Assembly is from any or all of the data acquisition pods, which exit the rear panel.
The user interface is from the-front-panel keyboard or with a controller via the
HP-IB or RS-232C connector on the rear panel. A more detailed theory of the
logic analyzer circuitry follows block level theory.
The CPU is a 68000 PlO microprocessor with addressing capability of 16
megabytes (23 address lines/l6 data lines). The CPU receives its clock (10 MHz)
from the TCL (Timing Control Logic). The TCL circuitry consists of
programmable array logic (PALS), various logic gates, and miscellaneous circuitry
for arbitrating between display and refresh requests of display and system RAM.
The PALS and arbitration circuitry are synchronized with a 20 MHz clock. The
rest of the circuitry is asynchronous. The signals generated by the TCL provide all
timing for the CPU. The CPU drives the read/write line and the address and data
strobes.
The CPU supplies a 2.5 MHz enable clock for synchronization with the CRT
Controller (CRTC).
The Oscilloscope Assembly contains the oscilloscope acquisition system. The
analog input to the Oscilloscope Assembly is from either or both of two channels,
located at the front-panel BNCs. The user interface is from the front-panel
keyboard or with a controller via the HP-IB or RS-232C connector on the rear
panel. A more detailed theory of the Oscilloscope Assembly follows the block
level theorv.
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Theory of Operation
HP
16526/1653B
6A-4
Service Manual