HP 1652B Getting Started Manual page 613

a. Move the cursor to the Pod Clock field, press SELECT, and assign
Demultiplex.
b. Move the cursor to the clock fields and assign the falling clock
transition of the J clock to the Master Clock and the rising J clock
transition to the Slave Clock.
c. Move the cursor to the appropriate bit field and assign ALL channels
to the pod under test (only bits 0 through 7 are available for
assignment).
d. Move the cursor to the Clock Period and set it to < 60 ns.
5. Set the State Trace Specification without sequencing levels and set Count
Off as in the previous figure 3-14.
6. Press RUN. The State Listing shows alternating Fs and OS for the pod under
test as in figure 3-29.
[ml- [State Llstlng ]
r I
tlarkers
Of1 j
Figure 3-29. State Listing for Data Test 6
IIC I
Note d
To ensure a consistent pattern of alternating Fs and OS, use the front-panel ROLL
field and knob to scroll through the State Listing.
7. Connect the next clock to the test connector and repeat steps 4 and 6.
8. Repeat steps 4,6, and 7 until all clocks have been tested (clocks J, K, L, M
and N).
9. Remove the probe tip assembly from the logic analyzer probe cable and
attach it to the next logic analyzer probe cable to be tested. Take care not to
dislodge grabbers from the test connector.
10. Repeat steps 3,4,6,7,8, and 9 until all pods have been tested (pods 1
through 5). Start with the falling edge of the J clock as the Master Clock and
rising edge of the J clock as the Slave Clock.
Performance Tests
3-26
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HP 16528/1653B
Service Manual