80186
Or
8OC186
CPU Package: 68.pin PGA
,-
HP 16528/1653B
Front-Panel Reference
Accessories Required: HP 10306G Preprocessor
Maximum Clock Speed:
12.5
MHz clock output (25 MHz clock input)
Signal Line Loading: Maximum of 100 kS2 + 18 pF on any line
Microprocessor Cycles Identified: Memory read/write (DMA and
non-DMA)
I/O read/write (DMA and
non-DMA)
Code fetch
Interrupt acknowledge
Halt acknowledge
Transfer to 8087,8089,
or 82586 co-processors
Additional Capabilities: The 80186 can be operating in Normal or
Queue Status modes. The logic analyzer can
capture all bus cycles (including prefetches)
or can capture only executed instructions.
Maximum Power Required: 0.08 A at + 5 Vdc, supplied system under
test.
Logic Analyzer Required: HP 1652B
Number of Probes Used: Four 16.channel probes
Microprocessor Specific Measurements
A-7