68030
CPU Package: ES-pin PGA
Accessories Required: HP 10316G
Maximum Clock Speed: 25 MHz input
Signal Line Loading: 100KQ plus 18 pF on all lines except DSACKO
and DSACKl.
Microprocessor Cycles Identified: User data read/write
User program read
Supervisor program read
Bus grant
Additional Capabilities:
CPU space accesses including:
Breakpoint acknowledge
Access level control
Coprocessor communication
Interrupt acknowledge
The logic analyzer captures all bus cycles,
including prefetches. The 68030
microprocessor must be operating with the
internal cache memory and MMU disabled
for the logic analyzer to provide inverse
assembly.
Maximum Power Required: None
Logic Analyzer Required: HP 1652B
Number of Probes Used: Five 16.channel probes
Microprocessor
Specific Measurements
A-16
HP 16528/1653B
Front-Panel Reference