HP 1652B Getting Started Manual page 204

Demultiplex
With the HP 1652B/l653B Logic Analyzers, you can clock two different
types of data that occur on the same lines. For instance, lines that
transfer both address and data information need to be clocked at
different times in order to get the right information at the right time.
When you select the Demultiplex option, the pod Clock field changes
to "Master 1 Slave," and two clock fields appear above the pods where
just one Clock field used to be. These fields are the Master Clock and
Slave Clock, as shown:
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tlsslsr Clock
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Clock Parlod
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Label Pal
El
Pod 5
1-1
---------w----w-
7 . . , . 07 . . . . 0
***I***-****.**+
(Sprcify Syrbols )
Slave Clock
I ut 1
Figure a-12. Master Clock and Slave Clock
Demultiplexing is done on the data lines of the specified pod to read
only the lower eight bits. This is two-phase clocking, with the Master
Clock following the Slave Clock. The analyzer first looks for the
clocking arrangement that you specify in the Slave Clock. When it sees
this arrangement, the analyzer clocks the data present on bits O-7 of the
pod, then waits for the clocking arrangement that you specify in the
Master Clock. When it sees this arrangement, it again clocks the data
present on bits O-7 of the pod. The upper eight bits of the pods are
ignored and don't need to be connected to your system.
Notice, the bit numbers that appear above the bit assignment field have
changed. The bits are now numbered 7 . . . . 07 . . . . 0 instead of l5 . . . . 87 . . . .
0 .
This helps you set up the analyzer to clock the right information at the
right time.
State Format Specification Menu
HP 1652B/l653B
940
Front-Panel Reference