HP 1652B Getting Started Manual page 203

With this arrangement, the state analyzer will clock the data when there
is a negative edge of the J clock OR a positive edge of the K clock,
AND when there is a low level on the M clock OR a high level on the N
clock.
You must always specify at least one clock edge. If you try to use only
clock levels, the logic analyzer will display a message telling you that at
least one edge is required.
Pod Clock
Your logic analyzer has the capability of clocking data in three
different ways. The pod Clock fields in the State Format Specification
menu. allow you to specify which of the three ways you want to clock the
data.
Each pod assigned to the state analyzer has a pod Clock field
associated with it. Selecting one of the pod Clock fields gives you the
following pop-up menu:
Figure 940. Pod clock Field Pop-Up Menu
Normal
This option specifies that clocking will be done in single phase. That is
the clocking arrangement located in the Clock field above the pods in
the State Format Specification menu will be used to clock all the pods
assigned to this machine.
For example, suppose that the Clock field looks like the following:
Clock
Figure 9-l
1.
Example of a Clocking Arrangement
HP
16528/l
6538
In Normal mode the state analyzer will sample the data on any assigned
pods on a negative edge of the J clock OR on a positive edge of the K
clock.
State Format Specification Menu
9-9