HP 1652B Getting Started Manual page 607

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State Listing

is displayed and shows alternating Fs and OS

for the channels under test as in figure 3-21.

Figure 3-21. State Listing for Data Test 4

To ensure a consistent pattern of alternating Fs and OS, use the front-panel ROLL

field and knob to scroll through the

State Listing.

7. Connect the next clock to the test connector and repeat steps 4 and 6 until all

clocks have been tested (clocks J, K, L, M, and N).

8. Remove the probe tip assembly from the logic analyzer probe cable and

attach it to the next logic analyzer probe cable to be tested. Take care not to

dislodge grabbers from the test connector.

9. Repeat steps 3,4,6 and 7 until the lower bits of all pods have been tested

(pods 1 through 5).

10. Disconnect the lower eight bits (bits 0 through 7) from the test connector and

attach the upper eight bits (bits 8 through 15) to the test connector.

11. Repeat steps 3,4,6,7,

and 8 until the upper bits of all pods (pods 1 through 5)

have been tested with all clocks.

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