HP 1652B Getting Started Manual page 610

a. Move the cursor to the Pod Clock field and press SELECT. Then
assign Mixed Clocks.
b. Move tlie cursor to the clock fields and assign the falling transition of
the J clock to the Master Clock and the rising transition of the J clock
to the Slave Clock.
c. Move the cursor to the appropriate bit assignment field and turn on
channels O-3 and
8-11
of the pod under test.
d. Move the cursor to the Clock Period and set it to < 60 ns.
5. Set the State Trace Specification without sequencing levels and Count Off
as in the previous figure 3-14.
6. Press RUN. The State Listing displays alternating Fs and OS for the channels
under test as in figure 3-25.
Label
Base t pj
+aooo 00
+oOOl
FF
+uoo2 00
+0003
FF
+0004 00
+ooos
FF
+0006 00
p?EJ
FF
+0008 00
+0009 FF
44010
WOll ;:
MO12 00
+0013
FF
+0014 00
MO15
FF
Figure
3-25.
State Listing for Data Test 5
IIC i
Note d
To
ensure a consistent pattern of alternating Fs and OS, use the front-panel ROLL
field and knob to scroll through the State Listing.
7. Connect the next clock to the test connector and repeat steps
4
and 6.
Repeat these steps until all clocks have been tested (clocks J, K, L, M, and
N) .
8. Remove the probe tip assembly from the logic analyzer probe cable and
attach it to the next logic analyzer probe cable to be tested. Take care not to
dislodge grabbers from the test connector.
9. Repeat steps 3,4,6, and 7 until channels 0 - 3 and 8 -
11
of all pods have been
tested (pods
1
through 5). Start with the falling edge of the J clock as the
Master clock and rising edge of the J clock as the Slave clock.
10.
Disconnect bits O-3 and bits 8-11 from the test connector and attach bits
4-7
and bits 12-15 to the test connector. Repeat steps 3,4,6,7, and 8 until all
pods have been tested (pods
1
through 5) with all clocks.
HP 1652B/1653B
Service Manual
Performance Tests
3-23