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Enhanced Queued Analog-to-Digital Converter (EQADC)
Table 25-37. Clock Divide Factor for Time Stamp (continued)
0b1110 - 0b1111
If TBC_CLK_PS is not set to disabled, it must not be changed to any other
value besides disabled. If TBC_CLK_PS is set to disabled it can be changed
to any other value.
25.5.3.3
ADC Time Base Counter Registers (ADC_TBCR)
The ADC Time Base Counter Register (ADC_TBCR) contains the current value of the time base counter.
ADC_TBCR can be accessed by configuration commands sent to CBuffer0 or to CBuffer1. A data write
to ADC_TBCR through a configuration command sent to CBuffer0 will write the same memory location
as when writing to it through a configuration command sent to CBuffer1.
Simultaneous write accesses from CBuffer0 and CBuffer1 to ADC_TBCR
are not allowed.
ADC0/1 Register address: 0x03
0
1
R
W
RESET:
0
0
= Unimplemented or Reserved
Figure 25-40. ADC Time Base Counter Register (ADC_TBCR)
1064
0b0011
0b0100
0b0101
0b0110
0b0111
0b1000
0b1001
0b1010
0b1011
0b1100
0b1101
Reserved
NOTE
NOTE
2
3
4
5
6
0
0
0
0
0
MPC5644A Microcontroller Reference Manual, Rev. 6
4
30
6
20
8
15
10
12
12
10
16
7.5
32
3.75
64
1.88
128
0.94
256
0.47
512
0.23
-
7
8
9
10
11
TBC_VALUE
0
0
0
0
12
13
14
15
0
0
0
0
0
Freescale Semiconductor
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