NXP Semiconductors MPC5644A Reference Manual page 1030

Enhanced Queued Analog-to-Digital Converter (EQADC)
Table 25-13. CFIFO0 Advance Trigger Operation Mode Table
AMODE0[0:3]
0b0000
0b0001
0b0010
0b0011
0b0100
0b0101
0b0110
0b0111 - 0b1111
25.5.2.8 EQADC Interrupt and DMA Control Registers (EQADC_IDCR)
The EQADC Interrupt Control Registers (EQADC_IDCR) contain bits to enable the generation of
interrupt or DMA requests when the corresponding flag bits are set in
Interrupt Status Registers
0 1
R
NCIE TORI
0 E0
W
RESET: 0 0
16 17
R
NCIE TORI
1 E1
W
RESET: 0 0
= Unimplemented or Reserved
Register address: EQADC_BASE+0x060
Figure 25-11. EQADC Interrupt and DMA Control Register 0 (EQADC_IDCR0)
1030
CFIFO0 Advance Trigger Operation Mode
Falling Edge External Trigger, Single Scan
Rising Edge External Trigger, Single Scan
Falling or Rising Edge External Trigger, Single Scan
(EQADC_FISR).
2 3 4 5 6
0
EOQ CFUI CFF
PIE0
IE0 E0 E0
0 0 0 0 0
18 19 20 21 22
0
EOQ CFUI CFF
PIE1
IE1 E1 E1
0 0 0 0 0
MPC5644A Microcontroller Reference Manual, Rev. 6
Disabled
Reserved
Reserved
Reserved
Reserved
Section 25.5.2.9, EQADC FIFO and
7 8 9 10 11
0 0 0 0
CFF
S0
0 0 0 0 0
23 24 25 26 27
0 0 0 0
CFF
S1
0 0 0 0 0
12 13 14 15
0
RFOI RFD RFD
E0 E0 S0
0 0 0 0
28 29 30 31
0
RFOI RFD RFD
E1 E1 S1
0 0 0 0
Freescale Semiconductor