Table 7.6.2C Interrupt Level Setting Bits And Interrupt Levels - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

[bit 11] or [bit 3] ISE
This is the EI
2
EI OS is activated if this bit is set to '1' and the interrupt sequence is activated if this bit is set to '0.' If
2
the EI OS end condition is satisfied (the S1 and S0 bits are not '00'), the ISE bit is cleared to '0.' If the
corresponding peripheral does not have the EI
This bit is initialized to '0' upon a reset.
[bits 10 to 8] or [bits 2 to 0] IL0, IL1, and IL2
These are interrupt level setting bits. Specify the interrupt level of the corresponding internal resource.
These bits can be read and written to. These bits are initialized to level 7 (no interrupt) upon a reset.
Table 7.6.2c describes the relationship between the interrupt level setting bits and interrupt levels.
IL2
MB90580 Series
2
OS enable bit. This bit can be read or written to. Upon issuance of an interrupt request,

Table 7.6.2c Interrupt level setting bits and interrupt levels

IL1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
7.6 Extended intelligent I/O service (EI2OS)
2
OS function, the software must set ISE to '0.'
IL0
0
0 (Highest interrupt level)
1 1
0
2
1 3
0
4
1 5
0
6 (Lowest interrupt level)
1 7 (No interrupt)
Level
Chapter 7: Interrupt 93