Clock Distribution Between Card Cages - Agilent Technologies 93000 SOC Series Training Manual

Mixed-signal training

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Lesson 1 – Analog Clock Domain Description

Not Connected

Clock generated by PLL

Clock forwarded from the

previous clock board

Clock Distribution between Card

This section summarizes the clock distribution between the card

cages of the testhead for the digital and for the analog clock

domain. In the previous section, the clock distribution to the slots

in an analog card cage was shown.

The clock boards of the card cages are the central points for the

clock distribution. They can generate clock signals, and distribute

these signals, or the clock signals from an AMC, to the slots and to

the clock boards of their neighbor cages.

The following diagrams show the clock distribution for the

available testhead configurations.

Clock Distribution 512 Testhead (no AMC, Digital Domain only)

In the figure above, the clock board in card cage 1 generates the

clock signal (master). The signal is distributed via Ring A to all

other clock boards (slaves).

Note: Although named Ring, the signal line A is not a closed loop.

Analog Card Cage

Analog Card Cage

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