Agilent Technologies 93000 SOC Series Training Manual page 83

100MHz Digitizer
The 100MHz Digitizer (software identifier: WDG) is a 105 Msps 14-
bit digitizer. This module has two signal paths with different A/D
converters. The respective signal paths are called the DC coupling
mode and AC coupling mode. The DC coupling mode is for
standard analog measurements and the AC coupling mode is for
high dynamic range analog measurements such as set-top-box
application. You can switch these modes according your test needs
when you set up a test. These modes share the pogo pins, input
multiplexer, sequencer, waveform memory as shown in the
following figure.
Mode Bandwidth
DC coupling mode DC - 100 MHz
AC coupling mode 250k - 100MHz
Input Multiplexer
Pogo Pin
A+ (16/Mode1)
B+ (14/Mode2)
C+ (12/Mode3)
D+ (10/Mode4)
A– (15/Mode5)
B– (13/Mode6)
C– (11/Mode7)
D– (09/Mode8)
AGND
SYNC CLK (04)
SYNC DATA (03)
DGND
(GND for SYNC CLK)
Block Diagram of WDG (Single-ended input routes shown with bold lines)
The WDG is a single-slot analog module installed in the testhead, and
has one digitizer core.
The single-ended signal or differential signal can be captured from
the pins shown in the following table.
Input
Single-ended input
Differential input
Lesson 1 – Analog Modules
Sampling Rate Resolution Waveform Memory
30 M - 105 Msps 14 bits
DC Coupling Mode R1: 37.5, 50, or 10k
R2: 100
+
R1 Input
Amp
R1 R2
-
Offset DAC
AC Coupling Mode
Filter
+
C 50
C 50
-
Filter
Timing
Generator
Master Clock
Possible Input Pin in Input Route of WDG
1 input only of 8 inputs:
A+, B+, C+, D+, A-, B-, C-, or D-
1 input only of 4 inputs:
A+&A- pair, B+&B- pair, C+&C- pair, or D+&D- pair
16 M samples
Filter ADC
Sequencer/
Waveform
Memory
Input
ADC
Amp
CCLK Stop/Sequencer Start
Conversion Clock (CCLK)
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