Agilent Technologies 93000 SOC Series Training Manual page 85

1GHz Digitizer (1 GHz Sampler 320 Msps Digitizer)
The 1GHz Digitizer module (software identifier: WDD) is the instru-
ment that contains a 1 GHz-BW 50 Msps 12-bit sampler and a 320
Msps 160 MHz-BW12-bit digitizer.
These sampler and digitizer are used alternatively; they share the
pogo pins, input multiplexer, sequencer, waveform memory, and A/
D converter as shown in the following figure. This figure shows
two offset DACs to simplify the diagram, however actually one
offset DAC (which sets the specified DC offset voltage) is shared in
both digitizer mode and sampler mode.
The sampler mode and digitizer mode can be used alternatively
even in a testsuite of the testflow. The default setting is digitizer
mode
Mode Bandwidth
Digitizer mode 160 MHz
Sampler mode 1 GHz
a
1 GHz bandwidth for using the pogo pin(s); C+, C-, D+, D-, C+&C-, or D+&D-.
900 MHz bandwidth for using pogo pin(s); A+, A-, B+, B-, A+&A-, or B+&B-.
Pogo Pin Input Multiplexer
A+ (16/Mode1)
B+ (14/Mode2)
C+ (12/Mode3)
D+ (10/Mode4)
A– (15/Mode5)
B– (13/Mode6)
C– (11/Mode7)
D– (09/Mode8)
AGND
SYNC CLK (04)
SYNC DATA (03)
DGND
(GND for SYNC CLK)
Block Diagram of WDD (Single-ended input routes shown with bold lines)
The WDD is a single-slot analog module installed in the testhead, and
has one digitizer/sampler core.
Lesson 1 – Analog Modules
Sampling Rate Resolution Waveform Memory
1M - 320 Msps
12 bits
a
1M - 50 Msps
Digitizer Mode R1: 37.5, 50, or 10k
R2: 100
+
R1 Input
Amp
R1 R2
-
Offset DAC
50
50
Offset DAC
Sampler Mode
Timing
Generator
Master Clock
4 M samples
Sequencer/
Filter
ADC
Waveform
Memory
+
S/H
Amp
-
In Sampler mode,
wider bandwidth for
C+/- and D+/- pin(s)
Conversion Clock (CCLK)
CCLK Stop / Sequencer Start
85