Agilent Technologies 93000 SOC Series Training Manual page 373

C. Cage 5
AMC
Master
(digital domain)
Ext.
Local PLL
External
RING A
NC
Ring
RING B
C. Cage 1
Slave
Ext.
Ring
RING A
Ring
RING B
NC
Not Connected
Local PLL
Clock generated by PLL
External
Clock from AMC
Clock forwarded from the
Ring
previous clock board
(analog domain)
C. Cage 3
Slave
NC Ext.
Ring
RING A
Ring
RING B
C. Cage 7
Slave
Ext.
Ring
RING A
Ring
RING B
Clock Distribution 1024 Testhead (with AMC, Digital Domain and Analog
Domain
The clock distribution and generation is the same as for the 512
testhead with AMC, except for the additional Ring B connections,
which operate exactly like the Ring A connections, and the fact
that the boards in cages 8, 2, 4 and 6 can operate as described
before for the boards 4 and 2 of the 512 testhead.
The 10 MHz Reference Clock
In addition to all the clock connections shown above, the clock
boards in all card cages of the test system are frequency locked by
a 10MHz reference clock signal which is distributed to all of them.
This reference signal is generated by a test system inherent
oscillator, if no AMC is installed. If an AMC is installed, the
reference signal is always generated by the AMC. The AMC
Lesson 1 – Analog Clock Domain Description
AMC
C. Cage 8
Slave
Ext.
Local PLL
External
Ring
RING A
Ring
RING B
Analog Card Cage
C. Cage 4
Slave
Ext.
Local PLL
External
Ring
RING A
Ring
RING B
Analog Card Cage
C. Cage 2
Slave
Ext.
Local PLL
External
Ring
RING A NC
Ring
RING B
Analog Card Cage
C. Cage 6
Slave
Ext.
Local PLL
External
Ring
RING A
Ring
RING B
Analog Card Cage
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