Agilent Technologies 93000 SOC Series Training Manual page 68

Mixed-signal training

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Lesson 1 – Analog Modules

The following figure shows the block diagram of the 30M AWG

(WGE); the bold lines show the single-ended output routes of the

The WGE is a single-slot analog module installed in the testhead,

and has two identical AWGs that share the trigger/timing system.

As shown in the following figure, the SYNC CLK pin (which is the

trigger input pin) and the timing generator are shared between its

Each AWG (called an AWG core) has the own waveform memory

and sequencer. Thus, the two AWG cores can generate different

waveforms and generate them with different waveform sequences.

Output Multiplexer

A+ (16/Mode1)

B+ (14/Mode2)

A– (15/Mode5)

B– (13/Mode6)

C+ (12/Mode3)

D+ (10/Mode4)

C– (11/Mode7)

D– (09/Mode8)

SYNC CLK (04)

SYNC DATA (03)

(GND for SYNC CLK)

Block Diagram of WGE (Single-ended Output Routes)

Both the AWG cores can be used simultaneously in multi-site

testing, cross-talk signal generation, IQ baseband signal generation,

or test application where the two signals are generated with the

common sampling rate and common trigger signal. You can differ

the start timing of the two AWG cores slightly by setting the trigger

delay parameter (max. 10 ns difference) plus the initial discard

parameter (max. 1023 sampling periods difference).

The single-ended signal and differential signal can be generated

from the pins shown in the following table.

Conversion Clock (CCLK)

CCLK Stop / Sequencer Start

Master Clock

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