Clock Sources And Clock Distribution Overview - Agilent Technologies 93000 SOC Series Training Manual

Lesson 3 – Setting up the Digitizers in the Digital Clock Domain
3-2
NOTE
Clock Sources and Clock
Distribution Overview
There are various options for the clock source that provides the
master clock signal (MCLK) to a clock domain. The availability of
these options depends on the test system configuration.
Every system has testhead internal clock boards. External clock
generators, called Alternate Master Clocks (AMC), are optional and
recommended for many mixed signal test applications because of
their higher clock signal quality.
Clock Sources for the Clock Domains
The DAC test you will run in this training will use digitizers that
run in the digital clock domain, with the testhead internal master
clock board as the source of the MCLK signal. This option is
highlighted in the above figure.
All other clock options, and how to set up analog modules using these
options, will be discussed in detail in Unit 5.
Each card cage of a testhead has a clock board, but only one of
these clock boards is the master board that generates the master
clock signal (MCLK). For the 512pin testhead the clock board in
cage 1 is the master, for the 1024pin testhead the clock board in
cage 5 is the master.
The clock signal is distributed from the master clock board to all
other clock boards. This is done via a clock line called Ring A
(plus Ring B line for the 1024pin testhead). All clock boards
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