Agilent Technologies 93000 SOC Series Training Manual page 297

Mixed-signal training

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The first code transition (from zero to one) of an ideal ADC occurs

at the analog equivalent of 0.5 LSB.

The last code transition (from 2

of bits) of an ideal ADC occurs at the analog equivalent of FS –

1.5 LSB. There are 2

Example: An 8-bit ADC tested in binary format covers a numerical

range from 0 to 255 (= 2

complement format would cover a numerical range from –128 to

+127. One LSB of this ADC is normally calculated as FS / 256.

The response of an ADC to an input voltage above FS – 0.5 LSB is

usually not defined.

Therefore, many ADCs have an additional voltage reference or

comparator and an additional output pin to signal overvoltage.

Some manufacturers consider that the first (zero) step and the last

step are only one half of a full width and therefore calculate:

1 LSB = FS / (2

– 1) for an n-bit converter.

Real ADCs show minor or major deviations from the ideal.

Binary Output Code

Analog Input

Ideal vs. Real ADC

A gain error, for example, would move the outer points further

out, an offset error would offset the whole curve.

Lesson 1 – The Training ADC

– 1 code transitions.

– 1). The same ADC operated in 2's

Binary Output Code

– 1, where n = number

Analog Input

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