Agilent Technologies 93000 SOC Series Training Manual page 625

Mixed-signal training
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AV DD
5 V
C1
J1
Video
Q1
Input
D1
R4
R1
– 5 V
NOTE A: Shorting JP1 and JP3 allows adjustment of the reference voltage by R5 using temperature-compensating diodes D2 and D3
which compensate for D1 and Q1 variations. By shorting JP2 and JP4, the internal divider generates a nominal 2-V reference.
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
APPLICATION INFORMATION
V REF
ADJ
FB3
FB2
R5
FB7
JP1
C3
TP1
R3
C11
FB1
R2
C5
C2
D3
C4
D2
JP3
JP4
TP3
LOCATION
C1, C3 – C4, C6 – C12
0.1-µF capacitor
C2
10-pF capacitor
C5
47-µF capacitor
FB1, FB2, FB3, FB7
Ferrite bead
Q1
2N3414 or equivalent
R1, R3
75-Ω resistor
R2
500-Ω resistor
R4
10-kΩ resistor, clamp voltage adjust
R5
300-Ω resistor, reference-voltage fine adjust
Figure 5. TLC5510 Evaluation and Test Schematic
POST OFFICE BOX 655303
SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003
C12
TLC5510
13
V DDD
14
V DDA
C8
15
V DDA
D8 (MSB)
C7
JP2
16
REFTS
17
REFT
C9
18
V DDA
C6
19
ANALOG IN
20
AGND
21
AGND
22
REFBS
C10
23
REFB
24
DGND
DESCRIPTION
DALLAS, TEXAS 75265
TLC5510, TLC5510A
Appendix D
DV DD
5 V
12
Clock
CLK
11
V DDD
C11
10
9
D7
8
D6
7
D5
6
D4
5
D3
4
D2
3
D1 (LSB)
2
DGND
1
Output
OE
Enable
625
9

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