Agilent Technologies 93000 SOC Series Training Manual page 81

Mixed-signal training

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20MHz Digitizer

The following figure shows the block diagram of the 20MHz

Digitizer (WDE); the bold lines show the single-ended input routes

The WDE is a single-slot analog module installed in the testhead,

and has two identical digitizers that share the sequencer, trigger

and timing system. As shown in the following figure, the

sequencer, the SYNC CLK pin (which is the trigger input pin) and

the timing generator are shared between its two digitizers.

Each digitizer (called a digitizer core) has the own waveform

memory. Thus, two digitizer cores can capture two analog signals

with a very tight timing skew (±1 ns characteristics if filter is

through and input range is same for both digitizer cores) for multi-

site test, IQ baseband signal measurement and so on.

Input Multiplexer

A+ (16/Mode1)

B+ (14/Mode2)

A– (15/Mode5)

B– (13/Mode6)

C+ (12/Mode3)

D+ (10/Mode4)

C– (11/Mode7)

D– (09/Mode8)

SYNC CLK (04)

SYNC DATA (03)

(GND for SYNC CLK)

Block Diagram of WDE (Single-ended Input Routes)

Lesson 1 – Analog Modules

Sampling Rate

Waveform Memory

125 ksps to 5 Msps

1 M samples (per digitizer core)

R1: 50 ohm or 1 Mohm

R2: used for differential input route

Conversion Clock

Seq Start / CCLK Stop

Master Clock

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