Agilent Technologies 93000 SOC Series Training Manual page 372

Lesson 1 – Analog Clock Domain Description
C. Cage 5
Master
NC Ext.
Local PLL
RING A
NC Ring
RING B
C. Cage 1
Slave
Ext.
Ring
RING A
Ring
RING B
NC
Not Connected
Local PLL
Clock generated by PLL
Clock forwarded from the
Ring
previous clock board
C. Cage 3
Slave
NC Ext.
Ring
RING A
Ring
RING B
C. Cage 7
Slave
Ext.
Ring
RING A
Ring
RING B
Clock Distribution 1024 Testhead (no AMC, Digital Domain only)
In the figure above, the clock board in card cage 5 generates the
clock signal (master). The signal is distributed via Ring A and Ring
B to all other clock boards (slaves).
Note: Although named Ring, the signal lines A and B are not
closed loops.
372
C. Cage 8
Slave
NC Ext.
Ring
RING A
Ring
RING B
Analog Card Cage
C. Cage 4
Slave
Ext.
Ring
RING A
Ring
RING B
Analog Card Cage
C. Cage 2
Slave
NC Ext.
Ring
RING A NC
Ring
RING B
Analog Card Cage
C. Cage 6
Slave
Ext.
Ring
RING A
Ring
RING B
Analog Card Cage