Agilent Technologies 93000 SOC Series Training Manual page 599

The THS5641A architecture is based on current steering, combining high update rates with low power
consumption. The CMOS device consists of a segmented array of PMOS transistor current sources, which are
capable of delivering a full-scale current up to 20 mA. High-speed differential current switches direct the current
of each current source to either one of the output nodes, IOUT1 or IOUT2. The complementary output currents
thus enable differential operation, canceling out common mode noise sources (on-chip and PCB noise), dc
offsets, even order distortion components, and increase signal output power by a factor of two. Major
advantages of the segmented architecture are minimum glitch energy, excellent DNL, and very good dynamic
performance. The DAC's high output impedance of >300 kΩ and fast switching result in excellent dynamic
linearity (spurious free dynamic range SFDR).
The full-scale output current is set using an external resistor R
voltage reference source (1.2 V) and control amplifier. The current I
internally to provide a full-scale output current equal to 32 times I
from 20 mA down to 2 mA.
data interface and timing
The THS5641A comprises separate analog and digital supplies, i.e. AV
supply voltage can be set independently from 5.5 V down to 3 V. The THS5641A provides two operating modes,
as shown in Table 1. Mode 0 (mode pin connected to DGND) supports a straight binary input data word format,
whereas mode 1 (mode pin connected to DV
Figure 23 shows the timing diagram. Internal edge-triggered flip-flops latch the input word on the rising edge
of the input clock. The THS5641A provides for minimum setup and hold times (> 1 ns), allowing for noncritical
external interface timing. Conversion latency is one clock cycle for both modes. The clock duty cycle can be
chosen arbitrarily under the timing constraints listed in the digital specifications table. However, a 50% duty cycle
will give optimum dynamic performance. Figure 24 shows a schematic of the equivalent digital inputs of the
THS5641A, valid for pins D7–D0, SLEEP, and CLK. The digital inputs are CMOS-compatible with logic
/2 ±20%. Since the THS5641A is capable of being updated up to 100 MSPS, the quality of
thresholds of DV
DD
the clock and data input signals are important in achieving the optimum performance. The drivers of the digital
data interface circuitry should be specified to meet the minimum setup and hold times of the THS5641A, as well
as its required min/max input logic level thresholds. Typically, the selection of the slowest logic family that
satisfies the above conditions will result in the lowest data feed-through and noise. Additionally, operating the
THS5641A with reduced logic swings and a corresponding digital supply (DV
Note that the update rate is limited to 67 MSPS for a digital supply voltage DV
APPLICATION INFORMATION
) sets a twos complement input configuration.
DD
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
8-BIT, 100 MSPS, CommsDAC
DIGITAL-TO-ANALOG CONVERTER
SLAS277A –MARCH 2000 – REVISED SEPTEMBER 2002
in combination with an on-chip bandgap
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through resistor R
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. The full-scale current can be adjusted
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and DV . The analog and digital
DD DD
) will reduce data feed-through.
DD
of 3 V to 3.6 V.
DD
THS5641A
Appendix C
is mirrored
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599
13