Agilent Technologies 93000 SOC Series Training Manual page 147

Analog modules start measurement or waveform generation after a
certain delay from the time the trigger signal is received. This
delay time is called trigger-to-signal delay. Each analog module
has a dedicated value of delay time.
The following table shows the fixed trigger-to-signal delay and the
accuracy in "( )".
Analog Module
High Resolution AWG (WGA)
b
30M AWG
(WGE)
High Speed AWG
(WGB)
500M AWG
(WGD)
Ultra High Speed AWG (WGC)
4.1G AWG (WGF)
e
High Resolution Digitizer (WDB) Digital/Analog 0 ns
20MHz Digitizer
(WDE)
High Speed Digitizer
(WDA)
f
100MHz Digitizer
(WDG)
1GHz Digitizer
(WDD)
Dual High Speed Sampler (SPA)
f
3GHz Sampler (SPB)
f
a
This value is satisfied if the filter is "through".
b
This value is satisfied if the filter is "through", the output voltage is 1 Vpp, and the DUT impedance
is 50 ohm.
c
If you do not set the compensation parameters, ±1 master clock period uncertainty is added to the
Trigger-to-Signal delay accuracy. For details, see the manual "System Reference".
d
OTA (Overall Timing Accuracy) is determined by the system model, P-Model (±200 ps) or C-Model/
Ce-Model (±350 ps).
e
For 4.1G AWG, Trigger-to-Signal Delay and Accuracy depend on the sampling rate. See the next table.
f
If you use the master/slave trigger function for SPAs, SPBs, or WDGs, the trigger-to-signal delay
changes according to the number of slave modules. See "Master/Slave Trigger Function" in Unit 8 for
details.
Lesson 3 – Synchronization of Analog Modules
Trigger-to-Signal Delay
Clock Domain
Digital/Analog 1000 ns (±250 ns ±1 master clock period)
Digital 160 ns (±5 ns)
Analog 160 ns (±5 ns ±1 master clock period)
Digital 200 ns (±1 ns)
Analog 200 ns (±1 ns ±1 master clock period)
Digital 200 ns (±1 ns)
Analog 200 ns (±1 ns ±1 master clock period)
Digital/Analog 110 ns (±450 ps + OTA ±1 sampling clock)
Digital/Analog X (± Y)
X=70.215 ns, Y=0.725 ns @4 Gsps, 500 MHz master clock
(±500 ns ±1 master clock period)
Digital 320 ns (±1 master clock period)
Analog 320 ns (±2 master clock period)
Digital 50 ns (±1 master clock period)
Analog 50 ns (±2 master clock period)
Digital 410 ns (±1 ns)
Analog 410 ns (±1 ns ±1 master clock period)
Digital 250 ns (±1 ns)
Analog 250 ns (±1 ns ±1 master clock period)
Digital 70 ns (±1 ns)
Analog 70 ns (±1 ns ±1 master clock period)
Digital 170 ns (±1 ns)
Analog 170 ns (±1 ns ±1 master clock period)
a
c
c
c
d
c
c
c
c
c
c
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